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Semiconductor History | SC17 Denver — NEC Fits a Vector Supercomputer Into a PCIe Card
· 2017-11
Personal memoryBy kevin · · Report an issue
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Semiconductor History | SC17 Denver — NEC Fits a Vector Supercomputer Into a PCIe Card
kevin
11/13/2017
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On 13 November 2017, the opening day of the SC17 exhibition in Denver, NEC displayed an SX-Aurora TSUBASA server with eight red Vector Engine cards. The photograph at this pin catches a Japanese vector-supercomputer lineage changing shape: what had once filled proprietary cabinets now fit into PCI Express slots beside an x86 Linux host.
Each first-generation Type 10A card carried a complete eight-core vector processor and up to 48 GB of HBM2. Six memory stacks joined the processor through CoWoS packaging, giving the card 1.2 TB/s of peak memory bandwidth and 2.45 teraflops of double-precision peak performance.
The good was architectural balance. Scientific codes often wait for data rather than arithmetic, so NEC paired unusually wide vector execution with memory placed close to the processor; an independent lattice-QCD study later confirmed the same 48 GB, 1.2 TB/s, and 2.45-teraflop specifications.
The card format also changed the business proposition. NEC could offer one Vector Engine in a deskside system or many in servers and racks, while the host handled Linux and operating-system work and the Vector Engine ran a complete application instead of merely accelerating a few kernels.
The bad was that “PCIe card” did not mean “drop-in GPU.” Useful performance still depended on code that vectorized well, NEC’s compiler and development stack, and attention to a processor whose 16-kilobit vector registers and separate high-bandwidth memory differed sharply from ordinary x86 programming.
That limited the ecosystem. The design preserved NEC’s expertise in custom vector silicon, but it did not create a commodity processor market; teams with irregular workloads or unmodified software could not assume that the headline bandwidth would become real speed.
SX-Aurora nevertheless outlived the launch generation. NEC’s current product page lists a third-generation Vector Engine, showing that the card strategy became a continuing product line rather than a one-conference demonstration.
The pin uses the photograph’s embedded coordinates at the Colorado Convention Center block. The image was taken at NEC’s SC17 booth and shows eight Vector Engines inside a transparent server, not a later rendering or a generic accelerator.
Sources: SC17, official exhibitor prospectus; NEC, 25 October 2017 launch release and technical attachment; NEC, current SX-Aurora TSUBASA Vector Engine page; Huth, Meyer, and Wettig, “Lattice QCD on a novel vector architecture,” 2020; OpenStreetMap Nominatim reverse record; Wikimedia Commons file metadata.
Photo: Vectoriser, CC BY-SA 4.0, via Wikimedia Commons. https://commons.wikimedia.org/wiki/File:8_VE_Aurora_TSUBASA_Server_transparent.jpg
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