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Semiconductor History | Intel Headquarters, 11 December 2018 — Foveros Stacks Logic on Logic
· 2018-12
Personal memoryBy kevin · · updated · Report an issue
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Semiconductor History | Intel Headquarters, 11 December 2018 — Foveros Stacks Logic on Logic
kevin
12/11/2018
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At its Architecture Day briefing on 11 December 2018, Intel disclosed Foveros, a packaging technology designed to stack active logic dies vertically. Intel presented it as its first three-dimensional logic-on-logic integration platform, extending chip construction upward rather than relying only on a larger flat die.
The good was architectural freedom. A compute die could sit above an active base die carrying input-output and power-delivery functions, joined through dense vertical connections, while designers selected different manufacturing processes for different layers.
That approach made physical disaggregation useful rather than merely necessary. Expensive leading-edge transistors could be reserved for functions that benefited from them, while other circuitry used processes better matched to cost, voltage, analog behavior, or availability.
Foveros entered products rather than remaining a slide-deck promise. Intel’s Lakefield processors moved into high-volume production with the technology, and later tiled processors made advanced packaging a visible part of Intel’s mainstream architectural strategy.
The bad was the complexity transferred into the package. Multiple active dies must be designed, fabricated, tested, aligned, connected, cooled, and supplied as one working product; a weakness in any element can affect cost, yield, scheduling, or performance.
Intel’s first Foveros product family did not establish a lasting mainstream franchise by itself. The durable achievement was the packaging capability, not proof that every early hybrid-processor choice built around it would succeed commercially.
Foveros consequently represents both reinvention and pressure. It gave Intel a credible tool for an era when one monolithic die was no longer always the best answer, yet it also acknowledged that future processors would depend on intricate assembly and, increasingly, a network of process technologies and suppliers.
The pin is Intel’s public headquarters and museum anchor. The 2018 technical briefing itself occurred at a non-public venue, so this memory does not expose or claim a private event address.
Image note: original technical-history illustration created for this memory; it is not a documentary photograph.
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